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Off-line manufacturing testing, defect tolerance and fault-tolerance
techniques are designed under the assumption that the system under test
is composed largely of correctly functioning units. This assumption is
severely tested in the case of emerging nanotechnologies such as
molecular electronics, quantum electronics, single electron transistors
and carbon nanotubes and nanowires. Self-assembly based device, circuit
and system level integration results in failures rates that are orders
of magnitude higher than traditional CMOS designs. In these emerging
technologies, fault and defect tolerance architectures -at the
physical, circuit and most importantly at the system level- are hence
an enabling technology for building reliable systems. The NANOARCH
workshop will investigate novel defect and fault tolerance
architectures suitable for highly unreliable nanotechnologies. The
workshop will be a forum for presenting theoretical, simulation and
case studies on new defect models, defect and fault tolerance
architectures, reliability models and experimental reliability
evaluation and validation frameworks related to defect and fault
tolerant nanoscale architectures and computer aided simulation and
design tools for these emerging nanotechnologies. Topics of interest
include but are not limited to:
- Failure modes in emerging nanoscale device technologies including
molecular electronics, quantum electronics, single electron
transistors, carbon nanotubes and carbon nanowires
- Defect and fault models for emerging nanoscale device technologies
- Circuit, Logic and System level Testing methodologies for Nanoscale Architectures
- Yield models, yield analysis and yield enhancement in nanoscale technologies.
- Device, Circuit, and System level Defect Tolerant Nanoscale Architectures
- Device, Circuit, and System level Fault Tolerant Nanoscale Architectures
- Emerging computational models for Nanotechnologies that consider reliability
- Novel Nanoscale Architectures that consider testing and reliability
- Dynamic reconfiguration in nanoscale architectures
- CAD for defect and fault-tolerant nanoscale systems
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The Program Committee invites authors to submit papers up to 8 pages in
length, describing original, unpublished recent work. Clearly describe
the nature of the work, explain its significance, highlight novel
features, and describe its current status. Electronic submission
through the workshop website is required.
The submission of a paper proposal will be considered evidence that
upon acceptance, the author(s) will present their paper at the
workshop. Final versions of accepted papers will be included in the
NANOARCH Workshop Digest.
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| Important deadlines: |
| Abstracts due: February 4, 2005 | Papers due: February 11, 2005 |
| Acceptance notification: March 20, 2005 | Final version due: April 8, 2005 |
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Sponsored by the IEEE Computer Society, Test Technology Technical Council.
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