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2nd IEEE International Workshop on
Defect and Fault Tolerant Nanoscale Architectures
(NANOARCH 2006) To be held in conjunction with the International Symposium on Computer Architecture June 17, 2006 Boston Park Plaza Hotel, Boston, MA, USA | |||||||
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Nanoarch 2007 Nanoarch 2005 Call for Papers ProgramNew Sign In GENERAL CHAIR R Karri, Polytechnic U PROGRAM CHAIR A Orailoglu, UC San Diego SPECIAL ISSUE CO-CHAIRS M. Stan, U Virginia K. Likharev, Stony Brook SPECIAL SESSIONS CHAIR Dan Hammerstrom, Portland State PUBLICITY C0-CHAIRS J. Chen, National Institute of Nanotechnology & U Alberta S. Levitan, U. Pittsburgh INDUSTRY LIAISON W. Joyner, SRC NANO TC LIAISON R Kapur, Synopsys ASIAN LIAISON K Kim, Incheon PUBLICATIONS CHAIR D. Sorin, Duke E-MEDIA CHAIR I Bayraktaroglu, Sun PROGRAM COMMITTEE Iris Bahar, Brown Valeriu Beiu, Washington State Shamik. Das, MITRE Andre DeHon, Caltech Chris Dwyer, Duke James Ellenbogen, MITRE Jose Fortes, Univ of Florida Haldun Hadimioglu, Polytechnic Niraj Jha, Princeton Alexander Khitun, UCLA Yusuf Leblebici, EPFL Meyya Meyyappan, NASA Ames Kaushik Roy, Purdue Alberto Sangiovanni-Vincentelli, UCB Sandeep Shukla, Virginia Tech Kang Wang, UC Los Angeles Kaijie Wu, UIC |
STUDENT TRAVEL GRANTS AVAILABLE: Please apply by June 8, 5:00 PM US Eastern Time, to indicate your interest in attending NanoArch by emailing NanoArch General Chair, Prof. Ramesh Karri (rkarri@duke.poly.edu) and Program Chair, Prof. Alex Orailoglu (alex@cs.ucsd.edu). Please indicate whether you will be presenting a paper at NanoArch. Decisions will be emailed by Friday, June 9, morning. Important deadlines:
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Current defect tolerance, fault-tolerance and manufacturing test techniques are designed under the assumption that a system under test is composed largely of correctly functioning units. However, this assumption is severely tested in emerging nanoelectronics such as molecular electronics, quantum electronics, single electron transistors and carbon nanotubes and nanowires. In these nanoelectronics, self-assembly based fabrication results in failures rates an order of magnitude higher than in traditional CMOS. Consequently, defect and fault tolerance -at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. NANOARCH will investigate novel defect and fault tolerance architectures targeting these highly unreliable nanoelectronics. The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, associated experimental reliability evaluation and validation frameworks and computer aided simulation and design tools for these emerging nanoelectronics. Topics of interest include but are not limited to:
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The Program Committee invites authors to submit papers up to 8 pages in length, describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. Electronic submission through the workshop website is required. The submission of a paper proposal will be considered evidence that upon acceptance, the author(s) will present their paper at the workshop. Final versions of accepted papers will be included in the NANOARCH Workshop Digest. | |||||||