NANOARCH '09
Full Program
Day
1—Thursday 30 July 2009
07:45 - 08:00 Continental Breakfast
08:00 - 08:15 Opening Remarks
08:15 - 09:45 Special Invited Session (Chair: Helen Li)
-
Swarup
Bhunia, Case Western
Reserve U.
Computing with Nanoscale Memory: Model
and Architecture
-
Yiran
Chen, Seagate Technology
Compact Modeling and Corner Analysis of
Spintronic Memristors
-
Patrick
Lincoln, SRI
Challenges in Scalable Fault Tolerance
09:45 – 10:45 Session I (Chair: Christof Teuscher)
-
Masoud
Hashempour, Zahra M. Arani, Fabrizio Lombardi
A Coding Framework for DNA Self-Assembly
-
Aaron Dingler, Michael Niemier, X. Sharon Hu,
Michael Garrison, M. Tanvir Alam
System-Level Energy and Performance Projections for Nanomagnet-Based Logic
10:45 - 11:00 Break
11:00 - 12:00 KEYNOTE (open to all DAC attendees)
Prof. Sandip Tiwari, Cornell
University
Computing Inexactly: A Potential Approach to Living with the Constraints
of the Nanoscale
12:00 - 01:30 Lunch
01:30 - 03:00 Panel: Emerging Technologies (Moderator: Helen Li)
(open to all DAC attendees)
Dr. Shekhar Borkar, Intel Dr.
Brian Lee, Seagate Technology
Dr. Myron Buer, Broadcom Mr.
Terry Ma, Synopsys
Dr. Norm Jouppi, HP Labs Dr.
Pol Marchal, IMEC
Dr. Benjamin C. Lee,
Microsoft Research
03:00 - 03:20 Break
03:20 - 05:30 Session II (Chair:
Michael Niemier)
-
Nor
Zaidi Haron, Said Hamdioui
Residue-Based Code for Reliable Hybrid Memories
-
Eero
Lehtonen, Mika Laiho
Stateful Implication Logic with Memristors
-
Pritish
Narayan, Kyoung Won Park, Chi on Chui, Csaba Andras Moritz
Validating Cascading of Crossbar Circuits With an Integrated Device-Circuit
Exploration
-
Saket
Srivastava, Aissa Melouki, Bashir M. Al-Hashimi
Repair Techniques for Defect Tolerance in Hybrid nano/CMOS Architecture
(short)
-
Inwook
Kong, Earl Swartzlander Jr., Seong-Wan Kim
Design of a Goldschmidt Iterative Divider for Quantum-Dot Cellular Automata
(short)
06:30 - 08:30 (Optional) Social Program
Day
2—Friday 31 July 2009
08:15 - 08:30 Continental Breakfast
08:30 - 10:30 Special Invited Session (Chair: Garrett Rose)
-
Prof.
Chi On Chui, UCLA
Cross-Wire FET Engineering for NASIC
Neuromorphic and Processor Applications
-
Dr.
Karlheinz Meier, Kirchhoff Institute
Neuromorphic Computing—Toward a
Biologically Relevant Scale
-
Prof.
Bernard Widrow, Stanford University
LMS Algorithm and the Memistor
-
Dr. Wei
Wu, HP Labs
Nanoimprint Lithography and Applications
10:30 - 11:00 Break
11:00 - 12:00 KEYNOTE (open to all DAC attendees)
Prof.
Bernard Widrow, Stanford University
"Cognitive" Memory and its Applications
12:00 - 01:30 Lunch
01:30 - 03:10 Session III (Chair:
Baris Taskin)
-
Yuan
Xie, Penn State Univ.
Power and Area Reduction Using Carbon
Nanotube Bundle Interconnect in Global Clock Tree Distribution Networks (Invited)
-
Tong
Zhang, RPI
Using Carbon Nanotubes in Digital
Memories (Invited)
-
Haigang
Yang, Sansiri Tanachutiwat, Wei Wang
FPGA Based on Integration of Carbon Nanorelays and CMOS Devices (short)
-
Ben
Kuiper and Sorin Cotofana
Adaptive Clock Scheduling for Pipelined Structures (short)
03:10 - 03:20 Break
03:20 - 05:00 Session IV (Chair:
Sorin Cotofana)
-
Pierre-Emmanuel
Gaillardon, Ian O'Connor, Junchen Liu, Fabien Clermidy
Interconnection Scheme and Associated Mapping
-
Adam C.
Cabe and Shamik Das
Detailed Performance Analysis of FPNI Nanocircuits
-
Yehua
Su, Wenjing Rao
Runtime Analysis for Defect-Tolerant Logic Mapping on Nanoscale Crossbar
Architectures (short)
-
Navid
Farazmand and Mehdi B. Tahoori
Online Detection of Multiple Faults in Crossbar Nanoarchitectures Using
Dual-Rail Implementations (short)
05:00 - 05:15 Presentation of NANOARCH 2009 Best Paper Award
Concluding Remarks