NANOARCH 2014

NANOARCH 2014 PROGRAM

	Tuesday - JULY 8, 2014
09:00 AM	Coffee & Breakfast
09:30 AM	Welcome and Introduction Jacques-Olivier Klein & Csaba Andras Moritz
09:40 AM	Session I: Memristive Circuits & Architectures Chair: Sarma Vrudhula
09:40 - 10:00	A Memristor-based TCAM (Ternary Content Addressable Memory) Cell Fabrizio Lombardi, Pilin Junsangsri, and Jie Han
10:00 - 10:20	On-Chip Supervised Learning Rule for Ultra High Density Neural Crossbar using Memristor for Synapse and Neuron Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, and Jacques-Olivier Klein
10:20 - 10:40	Sneak Paths Effects in CBRAM Memristive Devices Arrays for Spiking Neural Networks David Roclin, Olivier Bichler, Christian Gamrat, and Jacques-Olivier Klein
10:40 - 11:00	On the Influence of Synaptic Weight States in a Locally Competitive Algorithm for Memristive Hardware Walt Woods, Jens Bürger, and Christof Teuscher
11:00 - 11:30	Coffee Break
11:30 AM	Session II: Magnetics & Spintronics I Chair: Jie Han
11:30 - 11:50	System-level Assessment and Area Evaluation of Spin Wave Logic Circuits Odysseas Zografos, Praveen Raghavan, Luca Amaru, Bart Soree, Rudy Lauwereins, Iuliana Radu, Diederik Verkest, and Aaron Thean
11:50 - 12:00	STT-MRAM based Low Power Synchronous Non-volatile Logic with Timing Demultiplexing Kejie Huang, Rong Zhao, and Yong Lian
12:00 - 12:10	Nanoscale Spin Torque Oscillators as key building blocks for future Systems on Chip Mircea Stan
12:10 - 12:20	Strain clocked nanomagnetic memory and information processing devices: Simulations and experimental progress towards ultra-energy efficient Hybrid Spintronics-Straintronics Noel D'Souza, Mohammad Salehi Fashami, Supriyo Bandyopadhyay, and Jayasimha Atulasimha
12:30-2:00PM	Lunch
2:00 PM	Session III: Memory Modeling & Design Chair: Weisheng Zhao
2:00 - 2:20 PM	Integration of Threshold Logic Gates with RRAM Devices for Energy Efficient and Robust Operation Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, and Sarma Vrudhula
2:20 - 2:30 PM	HSPICE Macromodel of a Programmable Metallization Cell (PMC) and its Application to Memory Design Fabrizio Lombardi, Jie Han, and Pilin Junsangsri
2:30 - 2:40 PM	Compression Architecture for Bit-write Reduction in Non-volatile Memory Technologies David Dgien, Poovaiah Palangappa, Nathan Hunter, Jiayin Li and Kartik Mohanram
2:40 - 2:50 PM	A New Tunnel-FET based RAM Concept for Ultra-Low Power Applications Mostafizur Rahman, Mingyu Li, Jiajun Shi, Santosh Khasanvis, and C. Andras Moritz
2:50 PM	Session IV: Magnetics & Spintronics II Chair: Jayasimha Atulasimha
2:50 - 3:10 PM	Analog-to-Stochastic Converter Using Magnetic-Tunnel Junction Devices Naoya Onizawa, Daisaku Katagiri, Warren Gross, and Takahiro Hanyu
3:10 - 3:30 PM	A Standard Cell Approach for MagnetoElastic NML Circuits Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, and Maurizio Zamboni
3:30 - 3:40 PM	Design and Analysis of Racetrack Memory Based on Magnetic Domain Wall Motion in Nanowires Nesrine Ben-Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Zhaohao Wang, and Dafine Ravelosona
3:40 - 4:00 PM	Poster Pitch (2 minutes per poster) Chair : Nicolas Locatelli
4:00-4:30 PM	Coffee Break
4:30-5:30 PM	Poster Session
	Minimization of a 2n-to-n Quantum BCD Priority Encoder Circuit Nusrat Jahan Lisa and Hafiz Md Hasan Babu Memristor Content Addressable Memory Wanlong Chen, Xiao Yang and Frank Wang A Tunable Cache for Approximative Computing Magnus Själander, Nina Shariati Nilsson, and Stefanos Kaxiras Robust Sequence Storage with Bistable Oscillators David Colliaux, Pierre Bessière and Jacques Droulez A CMOS-Memristive Self- Learning Neural Network for Pattern Classification Applications Melika Payvand, Justin Rofeh, Avantika Sodhi, and Luke Theogarajan Sub-Crosspoint RRAM Decoding for Improved Area Efficiency Ravi Patel and Eby G. Friedman Volatile Memristive Devices as Short-Term Memory in a Neuromorphic Learning Architecture Jens Bürger and Christof Teuscher Pipeline Design in Spintronic Circuits Nickvash Kani and Azad Naeemi A Model for Variation- and Fault-Tolerant Digital Logic using Self-Assembled Nanowire Architectures Alireza Goudarzi, Matthew R. Lakin, Darko Stefanovic and Christof Teuscher NBTI Aware IG-FinFET based SRAM Design using Adaptable Trip-Point Sensing Technique Shikha Jain, Nandakishor Yadav, Manisha Pattanaik and G.K. Sharma
5:30 PM	End of Technical Session on the First Day
	Wednesday - JULY 9, 2014
09:00 AM	Coffee & Breakfast
09:30 AM	Session V: Emerging Devices Chair: Mircea Stan
09:30 - 09:50	Molecular Transistor Circuits: From Device Model to Circuit Simulation Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Guido Masera, Danilo Demarchi, Mariagrazia Graziano, and Gianluca Piccinini
09:50 - 10:00	Monte Carlo Simulations of Carbon Nanotube Networks for Optoelectronic Applications Miguel Diez-Garcia, Adrien F. Vincent, Nicolas Izard, and Damien Querlioz
10:00 - 10:10	Hysteresis-free Carbon Nanotube Field-Effect Transistors without Passivation Jana Tittmann, Sascha Hermann, Stefan E. Schulz, Anibal Pacheco-Sanchez, Martin Claus, and Michael Schröter
10:10 - 10:20	A Low Contact Resistance Graphene Field Effect Transistor with Single-Layer-Channel and Multi-Layer-Contact Honghui Sun, Liang Fang, Yao Wang, Yaqing Chi, and Rulin Liu
10:20 AM	Session VI: Keynote Address Graphene and 2D materials: Applications to conventional and emerging devices and circuits - Henri Happy (PDF Abstract) Chair: Jacques-Olivier Klein
11:20 - 11:50	Coffee Break
11:50 AM	Session VII: NEMs Based Circuits & Systems Chair: Damien Querlioz
11:50 - 12:10	Floating-Point Unit Design with Nano-Electro-Mechanical (NEM) Relays Sumit Dutta and Vladimir Stojanovic
12:10 - 12:30	Energy Effective 3D Stacked Hybrid NEMFET-CMOS Caches Mihai Lefter, Marius Enachescu, George Razvan Voicu, and Sorin Cotofana
12:30-2:00PM	Lunch
3:00 - 6:00 PM	Social Event - Guided Walking Tour in Paris “The Marais District” or “Voyage to the Heart of Paris”
7:45 - 11:00 PM	Dinner Cruise on the Seine
11:00 PM	End of the Second Day
	Thursday - JULY 10, 2014
09:00 AM	Coffee & Breakfast
09:30 AM	Session VIII: Reliability and Variability Chair: Paul Prucnal
09:30 - 09:50	Probability Density Function Based Reliability Evaluation of Large-Scale ICs Nicoleta Cucu Laurenciu and Sorin D. Cotofana
09:50 - 10:00	Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani and Giovanni De Micheli
10:00 - 10:10	Stochastic Reliability Evaluation of Sea-of-Tiles Based on Double Gate Controllable-Polarity FETs Catherine Dezan and Sara Zermani
10:10 AM	Session IX: Alternative Computing Paradigms Chair: Catherine Dezan
10:10 - 10:30	Wave-based Multi-valued Computation Framework Santosh Khasanvis, Mostafizur Rahman, Sankara Narayanan Rajapandian and Csaba Andras Moritz
10:30 - 10:40	Applications of Wavelength-fan-in for High-performance Distributed Processing Systems Alexander Tait and Paul Prucnal
10:40 - 10:50	Virtual Prototyping of R2DNasic based FPGA Ciprian Teodorov and Loic Lagadec
11:00 - 11:30	Coffee Break
11:30 AM	Closing Remarks Jacques-Olivier Klein & Csaba Andras Moritz
12:30-2:00PM	Lunch
2:00 PM	End of the Conference