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Important Deadlines:

Submission Deadline:
March 29, 2010

April 5, 2010
Acceptance Notification:
May 10, 2010
Final Version Due:
May 26, 2010
Early Registration:
May 17, 2010


Related Conferences



 

 


Thanks for a successful NANOARCH 2010!

NANOARCH 2011 will be held in San Diego, CA, USA! Click here for more info.

Congratulations to the winners of the NANOARCH 2010 Best Paper Award:
Michele De Marchi, M. Haykel Ben Jamaa, and Giovanni De Micheli!


NANOARCH 2010 is Co-located with the 47th Design Automation Conference (DAC)

    NANOARCH is the annual forum for the presentation and discussion of novel nanoelectronic circuit and system architectures. The NANOARCH symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century–how to design, fabricate, and test circuits and systems that will have to rely upon devices beyond conventional CMOS. In particular, such systems will (1) contain anywhere from a hundred to a trillion unconventional nanodevices with unique functionalities, (2) need to cope with unavoidably high levels of defects and faults, and (3) require rethinking of the methodologies involved, from the construction of basic logic gates / functional units to the compilation and mapping of high-level programs onto novel nanoscale computational fabrics.

    This 6th symposium seeks to build on the successes of the previous five iterations of NANOARCH (2005-2009). The symposium’s topics of interest include (but are not limited to) the following:

    • Ideas for novel nanoelectronic circuits or system architectures that resolve key issues anticipated in the design, fabrication, and operation of nanoelectronic systems
    • Performance simulations of nanoscale architectures, macro blocks, or key nanocircuits
    • Novel implementations of microarchitecture concepts using nanoscale building blocks
    • Computational paradigms and programming models for nanoscale architectures
    • Methodologies for incorporating defect and fault tolerance
    • Validation frameworks for ensuring correct functionality in defective nanoscale fabrics
    • Computer aided design tools and methodologies for nanoelectronic architectures
    • Experimental assessment and/or validation of nanoscale architectural concepts
We sincerely hope you can participate in NANOARCH 2010. Should you have any questions, please contact us using the links to the left.

    Proceedings from the previous NANOARCH symposiums are available online at IEEE Xplore

    Final versions of accepted papers will be included in official NANOARCH symposium proceedings.


    Symposium Sponsors: