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Day 1: Thursday, June 17,
2010 |
8:30-8:45 |
Continental Breakfast |
8:45-9:00 |
Welcome and Introduction |
9:00-10:20 |
Session I (Chair: TBD) |
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Compact Method for Modeling
and Simulation of Memristor Devices (Invited) |
|
Dr. Robinson E. Pino, AFRL |
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Stochastic Computation With
Lattices (Invited) |
|
Prof. Marc Riedel, U. Minn. |
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Memristor based Programmable
Threshold Logic Array (short) |
|
Jeyavijayan Rajendran,
Harika Manem, Ramesh Karri, and Garrett S. Rose |
10:20-10:40 |
Break |
10:40-12:20 |
Session II (Chair: TBD) |
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Toward Logic Fuctions as the
Device |
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Prasad Shabadi, Alexander
Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, and C.
Andras Moritz |
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High Throughput and Low
Power Dissipation in QCA Pipelines using Bennett Clocking |
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Marco Ottavi, Salvatore
Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter Kogge, and Fabrizio
Lombardi |
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Fast Equivalence-checking
for Quantum Circuits (short) |
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Shigeru Yamashita and Igor
L. Markov |
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Design and Comparison of NML
Systolic Architectures (short) |
|
Michael Crocker, X. Sharon
Hu, and Michael Niemier |
12:20-1:30 |
Lunch |
1:30-2:30 |
Keynote:
Kerry Bernstein, IBM
Post-CMOS Nanoarchitectures: A Benchmarking Perspective
(open to all DAC attendees) |
2:30-2:45 |
Break |
2:45-4:05 |
Session III (Chair: TBD) |
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UNION: A Unified
Inter/Intra-Chip Optical Network for Chip Multiprocessors (Invited) |
|
Prof. Jiang Xu, HKUST |
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Fault Modeling for FinFET
Circuits |
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Muzaffer O. Simsir, Ajay
Bhoj, Niraj K. Jha |
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Reducing transistor count in
clocked standard cells with ambipolar double-gate FETs (short) |
|
K. Jabeur, D. Navarro, I.
O'Connor, P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy |
4:05-4:30 |
Break |
4:30-5:30 |
PANEL: CAD for
Nanoelectronics |
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End of Day 1 |
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Day 2: Friday, June 18, 2010 |
8:15-8:30 |
Continental Breakfast |
8:30-10:20 |
Session IV (Chair: TBD) |
|
NanoV: Nanowire-Based VLSI
Design |
|
Muzaffer O. Simsir, Niraj K.
Jha |
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Artificial Nanoscale Ionic
Channels (Invited) |
|
Prof. Luke Theogarajan, UCSB |
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Nanoscale Neuromorphic
Circuits (Invited) |
|
Prof. Yong Chen, UCLA |
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Stochastic Nanoscale
Addressing for Logic (short) |
|
Eric Rachlin and John E.
Savage |
10:20-10:40 |
Break |
10:40-12:00 |
Session V (Chair: TBD) |
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Regular Fabric Design with
Ambipolar CNTFETs for FPGA and Structured ASIC Applications |
|
Michele De Marchi, M. Haykel
Ben Jamaa, and Giovanni De Micheli |
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Design Methodology for
Carbon Nanotube based Circuits in the Presence of Metallic Tubes |
|
Rehman Ashraf, Rajeev K.
Nain, Malgorzata Chrzanowska-Jeske, and Siva G. Narendra |
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Intel LVS Logic as a
Combinational Logic Paradigm in CNT Technology (short) |
|
Bao Liu, Zen Cao, Jun Tao,
Xuan Zeng, Pushan Tang, Philip H.-S. Wong |
|
|
12:00-12:15 |
Presentation of NANOARCH
2010 Best Paper Award
Concluding Remarks |
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